1. Field of the Invention
A double-conversion television tuner includes a Delta-Sigma Fractional-N Phase Lock Loop (PLL) to generate the first local oscillator signal. This arrangement permits finer frequency resolution with reduced phase noise, compared to existing approaches.
2. Background Art
In a double-conversion tuner, there are two local oscillators (LOs). It is possible to relax the requirements for each PLL by making the first LO cover a wide range in coarse steps, and the second LO cover only a narrow range but with all of the desired frequency resolution. The first and second LOs can be implemented using integer-N PLLs.
There is a fundamental tradeoff in integer-N PLLs between frequency resolution and phase noise performance. Generally, in an integer-N single-loop PLL, the loop bandwidth must be set to less than about one-tenth of the frequency step size in order to avoid stability problems. These problems arise because phase detectors used in PLLs generally sample the phase error at the reference frequency rate, which is equal to the step size in this type of PLL. Feedback control systems approach instability as the sampling rate is reduced towards the loop bandwidth. However, lowering the PLL loop bandwidth beyond some optimum point for compatibility with a lower sampling rate will increase the phase noise of the PLL, as the feedback action becomes progressively less able to track VCO phase fluctuations.
Various techniques have been developed to circumvent this limitation. One approach is to use multiple-loop PLLs as shown in FIG. 2. In these PLLs, the main loop 202 has only coarse frequency resolution. The feedback from the VCO 206 to the phase detector 204 is offset in frequency (using mixers 210 and filters 208) with the output of one or more additional PLLs 212 having fine frequency resolution. These additional PLLs 212 will generally cover a much smaller frequency range, or operate at much lower frequencies than the main loop 202. In this way, they can have reduced phase noise compared to a single-loop PLL covering the full desired range with fine resolution. The output frequency of the composite loop will be the reference frequency multiplied by the feedback divider ratio 214 in the main loop 202, summed with the offsetting terms from the additional PLLs 212.
Another class of techniques involves dithering the feedback divider modulus of a single-loop PLL. In this way, an average feedback modulus that is intermediate between two integers can be obtained. The problem to overcome in these approaches is the phase modulation introduced on the PLL output due to dithering. FIG. 3 illustrates one common technique to remove this unwanted phase modulation. In FIG. 3, a dithering circuit 306 generates a canceling signal for the known modulation present at the output of the phase detector 302. This can be accomplished by driving a digital-to-analog converter (DAC) 304 with an appropriate digital signal related to the dithering pattern, and summing the DAC 304 output (with appropriate phasing) with the phase detector 302 output. To be effective, however, the DAC 304 and phase detector 302 transfer functions have to be linear and matched to a high degree.
In a double-conversion tuner, there are two LO signals that can be generated by corresponding PLLs. It is possible to relax the requirements for each PLL by making the first LO cover a wide range in coarse steps, and the second LO cover only a narrow range in fine steps but with all of the desired frequency resolution.
The coarse-fine approach, although capable of providing good phase noise performance, is still somewhat limited by the need for fine frequency resolution in the second LO. The multiple-loop approach is disadvantageous because of its complexity. What is needed is a PLL for a double-conversion tuner that permits finer frequency resolution with reduced phase noise, compared to existing approaches.